Background
Jadeja, Vijaysinh Sardarsinh was born on February 2, 1955 in Gondal, Gujarat, India. Son of Sardarsinh Kalaji and Mahendrakumari Sardarsinh (Rana) Jadeja.
machinery design and development executive
Jadeja, Vijaysinh Sardarsinh was born on February 2, 1955 in Gondal, Gujarat, India. Son of Sardarsinh Kalaji and Mahendrakumari Sardarsinh (Rana) Jadeja.
Bachelor of Engineering in Mechanical Engineering, Lalbhai Dalpatbhai College Engineering, Ahmedabad, India, 1977.
Design engineer SLM-Manekual Industries Ltd., Ahmedabad, 1977-1979. Project engineer Physical Research Laboratory, 1979-1980. Project coordinator Ahmedabad Textile Industry's Research Association, since 1980.
Member Computer Society India, Textile Association India (member weaving committee), Institute Engineers India.
Married Mrudula Vijaysinh Jadeja, February 13, 1992. Children: Mittal Vijaysinh, Shailendra Vijaysinh.