Background
Agrawal, Vishwani Deo was born on February 7, 1943 in Allahabad, Uttar-Pradesh, India. Son of Basudeo Sahai and Prem Sahai (Prem Lata) Agrawal. came to the United States, 1967.
(Concurrent simulation is over twenty years old. During th...)
Concurrent simulation is over twenty years old. During that pe riod it has been widely adopted for the simulation of faults in digital circuits, for which it provides a combination of extreme efficiency and generality . Yet, it is remarkable that no book published so far presents a correct and sufficiently detailed treatment of concurrent simulation. A first reason to welcome into print the effort of the authors is, therefore, that it provides a much needed account of an important topic in design automation. This book is, however, unique for sev eral other reasons. It is safe to state that no individual has contrib uted more than Ernst Ulrich to the development of digital logic simulation. For concurrent simulation, one may say that Ernst has contributed more than the rest of the world. We would find such a claim difficult to dispute. The unique experience of the authors con fers a special character to this book: It is authoritative, inspired, and focused on what is conceptually important. Another unique aspect of this book, perhaps the one that will be the most surprising for many readers, is that it is strongly projected towards the future. Concurrent simulation is presented as a general experimentation methodology and new intriguing applications are analyzed. The discussion of multi-domain concurrent simulation-- recent work of Karen Panetta Lentz and Ernst Ulrich---is fascinat ing.
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(References . . . . . . . . . . . . . . . . . . . . . . . ...)
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . 147 12. 3. 2 Circuit Modeling 148 12.
http://www.amazon.com/gp/product/1461367670/?tag=2022091-20
(Concurrent simulation is over twenty years old. During th...)
Concurrent simulation is over twenty years old. During that pe riod it has been widely adopted for the simulation of faults in digital circuits, for which it provides a combination of extreme efficiency and generality . Yet, it is remarkable that no book published so far presents a correct and sufficiently detailed treatment of concurrent simulation. A first reason to welcome into print the effort of the authors is, therefore, that it provides a much needed account of an important topic in design automation. This book is, however, unique for sev eral other reasons. It is safe to state that no individual has contrib uted more than Ernst Ulrich to the development of digital logic simulation. For concurrent simulation, one may say that Ernst has contributed more than the rest of the world. We would find such a claim difficult to dispute. The unique experience of the authors con fers a special character to this book: It is authoritative, inspired, and focused on what is conceptually important. Another unique aspect of this book, perhaps the one that will be the most surprising for many readers, is that it is strongly projected towards the future. Concurrent simulation is presented as a general experimentation methodology and new intriguing applications are analyzed. The discussion of multi-domain concurrent simulation-- recent work of Karen Panetta Lentz and Ernst Ulrich---is fascinat ing.
http://www.amazon.com/gp/product/0792394119/?tag=2022091-20
(References . . . . . . . . . . . . . . . . . . . . . . . ...)
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . 147 12. 3. 2 Circuit Modeling 148 12.
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electrical engineer computer scientist
Agrawal, Vishwani Deo was born on February 7, 1943 in Allahabad, Uttar-Pradesh, India. Son of Basudeo Sahai and Prem Sahai (Prem Lata) Agrawal. came to the United States, 1967.
Bachelor of Science, Allahabad (India) University, 1960. Bachelor Engineering, Roorkee (India) University, 1964. Master Engineering, Indian Institute of Science, Bangalore, 1966.
Doctor of Philosophy, University Illinois, 1971.
Associate lecturer, Indian Institute Technology, New Delhi, 1966-1967; graduate assistant, University of Illinois, Urbana, 1967-1970; engineer, Automation Technology Inc., Champaign, Illinois, 1970-1971; senior scientist, Edgerton, Germeshauser, and Greer Inc., Albuquerque, New Mexico, 1971-1972; assistant professor, Indian Institute Technology, New Delhi, 1972-1975; member technical staff, TRW Defense & Space Systems Group, Redondo Beach, California, 1975-1978; member technical staff, American Telephone & Telegraph Company Bell laboratories, Murray Hill, New Jersey, 1978-1982; supervisor, American Telephone & Telegraph Company Bell laboratories, Murray Hill, New Jersey, 1982-1986; member technical staff, American Telephone & Telegraph Company Bell laboratories, Murray Hill, New Jersey, 1986-1990; Distinguished member technical staff, American Telephone & Telegraph Company Bell laboratories, Murray Hill, New Jersey, since 1990. Member technical advisory board Gateway Design Automation Corporation, Lowell, Massachusetts, 1988-1990. General co-chairman 4th International Computer Society of India/Institute of Electrical and Electronics Engineers Symposium on Very-large-scale integration Design, New Delhi, India, 1991.
(Concurrent simulation is over twenty years old. During th...)
(Concurrent simulation is over twenty years old. During th...)
(References . . . . . . . . . . . . . . . . . . . . . . . ...)
(References . . . . . . . . . . . . . . . . . . . . . . . ...)
Fellow Institute of Electrical and Electronics Engineers, Institution Electronics and Telecommunication Engineers (India). Member Institute of Electrical and Electronics Engineers Antennas and Propagation Society (Best Applications Paper award 1979), Institute of Electrical and Electronics Engineers Computer Society (Best Paper award International Test Conference 1982, Best Presentation award International Conference Computer Design 1985, 88, Meritorious Service award 1989), Association for Computing Machinery, Very Large Scale Integration Society India (honorable mention 5th International Conference on Very-large-scale integration Design 1992, chairman conference steering committee since 1992).
Married Prathima Arakere, June 8, 1968. Children: Vikas, Chitra.