Background
Yeo, Kiat Seng was born on March 29, 1964 in Singapore. Son of Kim Chiang and Geok Baw Oei.
(Offers thorough coverage of predicting and managing BiCMO...)
Offers thorough coverage of predicting and managing BiCMOS circuit delay time and power dissipation sensitivites. Offers a convenient, reliable solution for calculating worst-case speed degradation given a set of device and process parameter tolerances. DLC: Metal oxide simiconductors.
http://www.amazon.com/gp/product/0130113808/?tag=2022091-20
consultant engineering educator
Yeo, Kiat Seng was born on March 29, 1964 in Singapore. Son of Kim Chiang and Geok Baw Oei.
Bachelor of Engineering with honors, Nanyang Technology University, Singapore, 1993. PhDEE, Nanyang Technology University, Singapore, 1996.
Engineer Toshiba Ptd Ltd., Singapore, 1988-1990. Lecturer Nanyang Technological University, 1996-1998, assistant professor, 1999—2002, sub-dean, since 2001, associate professor, since 2002, head circuits and systems, since 2005. Integrated circuit design coordinator Nanyang Technological University, Singapore, since 1999, program manager, since 2000, IC technical coordinator, since 1999, technical chairman 8th and 9th international symposium on integrated circuits devices and systems, since 1999.
Consultant semiconductor devices and electronic circuit design for multinational corporations.
(Offers thorough coverage of predicting and managing BiCMO...)
Senior corporal Head Qtrs. Navy, Singapore, 1984-1987. Member of Institute of Electrical and Electronics Engineers.
Married Ah Cheng Ong, March 8, 1994. Children: Shun-Yuan, Shun-Yi, Shun-Yu, Shun-Fei.