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Yoshihisa Nagano Edit Profile

Semiconductor engineer

Yoshihisa Nagano, Japanese semiconductor engineer. Achievements include development of Ferro-electric Random Access Memory embedded system LSIs. Recipient Excellent Patant, Ministry of Education, Sports, Science and Technology, 2000. Member of Japanese Society Applied Physics (associate).

Background

Nagano, Yoshihisa was born on August 21, 1966 in Fukuoka City, Japan. Son of Shigekazu and Tomiko Nagano.

Education

Master of Electrical Engineering, Osaka University, 1991.

Career

Clerk Matsushita Electric Industrial Limited company, Takatsuki, Japan, 1991—1994, engineer, 1995—1999, staff engineer Kyoto, 2000—2004, chief engineer, since 2005. Member VSLI project team Matsushita Electric Industrial Limited company, leader VSLI project, since 2004. Presenter to conferences.

Achievements

  • Achievements include development of Ferro-electric Random Access Memory embedded system LSIs.

Membership

Member of Japanese Society Applied Physics (associate).

Connections

Married Ayumi Nagano, April 9, 1994.

father:
Shigekazu Nagano

mother:
Tomiko Nagano

spouse:
Ayumi Nagano